Vhdl verilog testbench trabalhos

I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

hey, I saw your work on the vhdl fm radio and I want to know if you're willing to send that same project.

The project goal is the implementation of a Verilog module to interface a high-speed ADC (250MSps) using DDR. The IO/delay shall be dynamically adjusted after reset thru a test pattern match using a test mode of the ADC. As part of the project a simulation test bench needs to be set-up to verify proper function of the interface.

Need a vhdl project on mips pipelined processor

Hi olegkaravaev84, I noticed your profile and would like to offer you my SystemVerilog/Verilog FP{GA project. We can discuss any details over chat.

We're looking for someone with experience is sending data from an FPGA to a PC via a FT601 chip (made by FTDI) and saving the data to a binary file on the PC side.

an expert on FPGA and Verilog should bid only...

I have one architecture, needs the RTL verilog code for the design to be made and followed by placement and routing to derive the power.

FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design

The brightness measurement with help of PMODALS sensor ( ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core() is to be used...at/products/ip-cores/8051-ip-core) is to be used, which takes over the control. The result of the brightness should be displayed on 7-segment displays. At lower or exceeded a threshold value (for example: 80%), all LEDs should ON. By pressing one of the push buttons, the display should change between the display modes percent (0% -100%) and ADC value (0-255). I can send to you all necessary vhdl files for mc8051. Keywords: VHDL, C, SPI, mc8051, Basys3, FPGA, Ambient light sensor

Hi Jin, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

build mac unit using verilog language. I have already done the multypler part and I need help to build the rest

...Development boards, design software and encoder hardware 4- Separate documents will be provided on use of this hardware and software. 5- You will use two approaches to design development. First you are required to produce a simple/minimal implementation using logic primitives (basic gates and flip flops). Secondly you are to produce a (more) fully capable design using VHDL. Both designs are to be verified by simulation. 6- The VHDL-based design should also be programmed into the FPGA on the development board and verified using the encoder hardware provided. More detailed specifications and requirements will be given to you later 7- The entire work mentioned above needs to be documented so if you do not have GOOD WRITTEN ENGLISH SKILLS please DO NOT apply. Thank you...

FPGA mining hardware - Xiling FPGA - Nexys Video - Can be leveraged from open source bitcoin miner code. - Based on Verilog. - Provide source code, constraints and full recipe for synthesis, implementation and bitstream generation - Connectivity via JTAG to the host (via USB). May consider UART instead, but as a less desirable solution. Mining software: bfgminer, cgminer or similar - Based on stratum protocol - Enable driver that connects to the mining hardware

I have a VHDL source for the Altera EP3C25F256C8 FPGA design. I like an expert to setup the timing and fitting parameters to give the design optimum performance. I use Quartus II software version 8.1

The distance measurement with help of MB1010 ultrasonic distance sensor ( ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core () is to...Furthermore, an 8051 microcontroller IP core () is to be used, which takes over the control. The result of the distance measurement should be displayed on 7-segment displays. Pressing a button on the board should switch between inches, meters and centimeters. I can send to you all necessary vhdl files for mc8051. Keywords: Basys3, FPGA, Ultrasonic distance sensor, UART, mc8051 IP Core, VHDL, C, Vivado, ModelSim

Using ModelSim or Quartus II for solving some problems i am working on

Hi Loi L., I noticed your previous work on the FIFO implementation of a FM Radio in VHDL. I was wondering if you would like to work on that same project. We can discuss any details over chat.

The details of the design will be sent and discussed later. The freelancer needs to have proficient knowledge of VHDL and digital design. Only serious and professional freelancers needed

I NEED VLSI CODE VHDL-7-5-Reed-Solomon ENCODER AND DECODER I HAVE SOME CODE JUST NEED TO RUN AND EXPLAIN MAKING SOME CORRECTIONS

The brightness measurement with help of PMODALS sensor ( ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core() is to be used, which takes over the contr...to be used, which takes over the control. The result of the brightness should be displayed on 7-segment displays. At lower or exceeded a threshold value (for example: 80%), all LEDs should flash. By pressing one of the push buttons the display should change between the display modes percent (0% -100%) and ADC value (0-255). I can send to you all necessary vhdl files for mc8051. Keywords: Basys3, FPGA, Ambient light sensor, SPI, mc8051, VHDL, C, Vivado

Code will contain encryption and decryption of elliptic curve cryptography

In this project, a simple VGA (Video Graphics Array) controller shall be implemented using an FPGA Basys3. The VGA controller should be able to display images with a resolution of 640X480 pixels. Furthermore, it should be possible to select between two different images, depending on the position of switch SW1. Document description of whole design including images explanation of Testbench with ModelSim IntelFPGA

Hi, we have project for creating simple RISC processor through vhdl/Verilog. If interested will give more information

VHDL/Verilog basic RISC Processor, will give more details if interested

This project consists to port some c code (around 50 lines) to Verilog in order to run on a FPGA. Output of the contest Verilog .v source file equivalent of verilog.c testbench .v file equivalent to doSimulation() You can run the C code with "gcc main.c && ./" Elements to select the winning bidder: - Partial screenshot of the implementation or snipset of the implementation - Any ideas, comments, remarks how to get the best implementation - How MIN2 and MAX2 is implemented - Approximate number of LUTs of the module - If a Lattice Diamond project is provided for the simulation. I use Lattice which is freely available at (including the simulator) - The code has been tested on a simulator (required) - The code has been tested on a FPGA (optional) - CV...

Hi, I need SPI master design in vhdl. Here is the data sheet. What I need is the functionality to read and write to SPI flash that is in the attached datasheet. I will give you $100 for it if you can successfully complete the project.

I need a detailed video tutorial which includes the following material: - A thorough tutorial with several examples on zedboard XADC. - A thorough tutorial with several examples showing: 1. reading an input analogue signal through XADC 2. processing it in "Xilinx System Generator" and 3. showing the re...the following material: - A thorough tutorial with several examples on zedboard XADC. - A thorough tutorial with several examples showing: 1. reading an input analogue signal through XADC 2. processing it in "Xilinx System Generator" and 3. showing the results on the oscilloscope. The video tutorial should be at least 1 hour. All files and scripts should be shared. The project should be done in VHDL code. The whole procedure must be done in details and quest...

-Tools:Altera Quartus,Modelsim and FPGA. -This Project is divided to two parts:- and implement a 32 bit architecture pipelined CPU with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x 32) 2- ALU 3- Instruction Register 4- Control Unit 5- PC register 6- Shift logic unit 7- Conditional logic unit 8- Three-level Cache for the Data Memory (reading and writing) 9- Data Memory 10- Branch target address adder In a 32 bit architecture CPU, for an opcode of 6 bits wide there should be 64 instructions. You are required to function the following 10 instructions from the 64. 1- add 2- sub 3- load 4- store 5- and 6- or 7- branch if zero

matrix multiplication using strassenalg and karatsuba alg and carry select adder

This job is ONLY for experienced FPGA - Verilog Programmers. Apply now if you have developed bitstreams for complex applications using Xilinx or Altera FPGAs. We will match your pay with your current income OR more than that (depends on qualification) + Bonus when you deliver expected results + Opportunity to work from home + Chance to work on exciting and growing Blockchain Technology + No contract. Job Requirement: - Most of job tasks are bound around Verilog programming and embedded systems. - Develop bitstream for different algorithms for variety of FPGA boards. - Code, simulate, synthesize and support to compile Verilog on FPGA. - Embedded Linux Development, VxWorks, RTEMS, or similar real-time operating systems. - C/C++, integrate software components, create a...

Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

General Information “Counter Unit”, “IO Control Unit”, “Top Level & Testbench” and “Synthesis & Implementation will give you additional information about each sub-module of the project in order to realize the counter. FOR ALL DETAILS PLEASE CHECK DIGITAL DESIGN. pdf !!! Functional Specification A four-digit counter shall be implemented for the Basys3 FPGA development board. The FPGA used is a Xilinx Artix-7 FPGA (XC7A35T-1CPG236C). An asynchronous high-active reset shall be used to initialize the design (BTNC button on the Basys3 board). The whole design uses a 100 MHz clock. One switch for the selection of the count direction (CNT_UP/CNT_DOWN). ‘1’ … count up, ‘0’ … count down. If the counter ...

need to use Quratz 18.1 to create and simulate a 5 bit counter.

Here projects are implemented in VHDL programming using Xilinx software. B.E/ Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

I am a Verilog beginner. Need help in instantiating a LUT based memory. The requirements are stated in the file.

Please read all the details first. an...milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting with (Equihash Varient or X16r (required chaining 2 together)? have you developed bistreams before? Please check all more details on word ...

Please read all the details first. an...milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting with (Equihash Varient or X16r (required chaining 2 together)? have you developed bistreams before? Please check all more details on word ...

Vivado 2016.1 will be used. Create a testbench and simulate it in ModelSim with the help of the already provided script files. Design a synchronous system in VHDL which controls a two-storied elevator (ground floor and first floor). You will implement it with a two-process FSM as described above. The clock signal has a frequency of 10 MHz. The circuit should be initialized with a high-active reset signal. After a reset the elevator is always situated at the ground floor. The controller has six inputs (in addition to clock and reset): Button GF inside the cabin to descend to the ground floor (gf_cab_i). Button F1 inside the cabin to ascend to the first floor (f1_cab_i). Button UP located on the ground floor to call the elevator cabin (gf_call_i). Button DOWN located on the f...

Digital Circuit will be represented and simulated via ModelSim simulator. Consider the digital circuit represented below. Two eight-bit wide data input ports are added. The result is then used t...Consider the digital circuit represented below. Two eight-bit wide data input ports are added. The result is then used to set one of eight output lines according to predefined thresholds. Code this design in VHDL and verify its correctness by writing a testbench. Simulate the design using the ModelSim simulator. What is the difference between the data type bit and the data type std_logic in VHDL? What is the difference between the data type bit_vector and the data type std_logic_vector in VHDL? What is the difference between VHDL signals and variables? Which da...

Please read all the details first. an...milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting with (Equihash Varient or X16r (required chaining 2 together)? have you developed bistreams before? Please check all more details on word ...

Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

You have to programming a stopwatch with an Memory function in VHDL. It has to run on a Nexy 4 - fpga Board. Best regards, Kevin

Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks

Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

...latest trends in the industry - Opportunity to work with experienced developers - Possibility to work closely with other teams - Receptivity to your own innovations and ideas - A young and well-coordinated small team - A nice and friendly working environment - Flexible working hours - Option to learn during working hours (the 90/10 rule) WE REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture WE PREFER: - Experience with HW synthesis tools for ASIC/FPGA - Knowledge of versioning tools (Git, SVN) - Ability to write clear and concise code - Active interest in the field and self-education...

I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks