Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Contratar Verilog / VHDL Designers

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    13 trabalhos encontrados, preços em EUR
    Verilog HDL 5 dias left

    building a simple hardware description of a sequential circuit in Verilog HDL which goal is to produce clock signals for serial communication baud rate generators.

    €74 (Avg Bid)
    €74 Média
    13 ofertas

    Need to implement different logics using primitives like IDELAYE3 / ODELAYE3 primitives to calculate delays accurately with few PS resolution.

    €249 (Avg Bid)
    €249 Média
    5 ofertas

    Hi, i have this coding about image processing using verilog that i took from here [fazer login para ver a URL] but i have a problem trying to make it synthesizable. Can you help me with that?

    €48 (Avg Bid)
    €48 Média
    8 ofertas

    Hello, I have an accelerometer (I2C) and I want to read it and print the output on the terminal through UART. The code must be written in Verilog or SystemVerilog targeting Xilinx FPGAs. It will be tested in a Digilent Cmod A7. Design: I2C Master <-> FSM <-> UART

    €144 (Avg Bid)
    €144 Média
    5 ofertas

    [fazer login para ver a URL] and research paper Explanation [fazer login para ver a URL] and PPT

    €123 (Avg Bid)
    €123 Média
    2 ofertas

    I need someone who can Implement optimized bitsteam for both card types cvp13 as well as bcu1525 .As well as DNA locked pc [fazer login para ver a URL] file. It should be a Bitsteam and miner application for both cvp13 and bcu1525. Kawpow algorithm minimum hashrate of 400mh for bcu and 650 for cvp I pay you 250 € after successful test From my experience guys are taking a pc miner version t...

    €194 (Avg Bid)
    €194 Média
    2 ofertas

    I have a verilog model for DLL and the model needs to modify it based on some requirements. This is simple task for the one who has a good background in this context but you will get benifit from continuing with me in this project

    €14 (Avg Bid)
    €14 Média
    4 ofertas

    - Comparing and analysis the performance of existing protocols such as Epidemic, Spray and Wait and PROPHET using ONE Simulator - Required to design and create new routing protocol based on existing protocols such as Epidemic, Spray and Wait and PROPHET protocols using ONE Simulator. - Implement and simulate the new routing protocol using ONE Simulator

    €148 (Avg Bid)
    €148 Média
    3 ofertas
    Vitis AI Coach 2 dias left
    VERIFICADO

    Searching for someone with experience in Vitis AI and various HLS optimization techniques. Please leave your hourly rate and experience with Vitis AI. Memory access and computation optimization.

    €27 / hr (Avg Bid)
    €27 / hr Média
    9 ofertas

    Anyone interest in building FPGA to mine bitcoin or other type of crypto currencies.

    €458 (Avg Bid)
    €458 Média
    5 ofertas
    Modify LimeSDR FPGA 21 horas left

    The LimeSDR-USB allows to either transmit signals at once or schedule them. In all cases the samples must be passed from the host to the device at each call, which can take time due to the USB speed and latency. We would like to be able to just tell the device to transmit a specific type of signal, either at once or at a specific timestamp, without passing the samples each time. The different sig...

    €2561 (Avg Bid)
    €2561 Média
    8 ofertas

    I have a circuit which needs to communicate to an external microprocessor.

    €34 (Avg Bid)
    €34 Média
    6 ofertas

    I need someone who knows verilog hdml, quartus and modelsim.

    €13 (Avg Bid)
    €13 Média
    2 ofertas