Vhdl verilog testbench trabalhos

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    2,929 vhdl verilog testbench trabalhos encontrados, preços em EUR

    Implementar um jogo em verilog ou vhdl em vga

    €124 (Avg Bid)
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    6 ofertas

    Jogo VGA em Verilog para FPGA

    €136 (Avg Bid)
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    3 ofertas
    VHDL/verilog Encerrado left

    Segue trabalho em anexo

    €130 (Avg Bid)
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    10 ofertas
    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

    €23 (Avg Bid)
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    3 ofertas

    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    €384 (Avg Bid)
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    2 ofertas
    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três está...

    €418 (Avg Bid)
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    3 ofertas

    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são

    €1828 (Avg Bid)
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    ...para formar uma palavra de 32 bits. Os sinais de controle m1, m2, m3, wPC, wMem, wRI devem ser associados às chaves de entrada. Um arquivo comprimido com todos os módulos VHDL do MIPS multiciclo é disponibilizado no Moodle. O código MIPS a ser carregado na memória está contido no arquivo mem.mif. Para exibição dos dados nos ...

    €85 (Avg Bid)
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    Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do c&...

    €274 (Avg Bid)
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    1 ofertas

    Here projects are implemented in VHDL programming using Xilinx software. B.E/[fazer login para ver a URL] Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

    €136 (Avg Bid)
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    2 ofertas

    I am a Verilog beginner. Need help in instantiating a LUT based memory. The requirements are stated in the [fazer login para ver a URL] file.

    €26 (Avg Bid)
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    8 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €667 (Avg Bid)
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    1 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €167 - €502
    €167 - €502
    0 ofertas

    Vivado 2016.1 will be used. Create a testbench and simulate it in ModelSim with the help of the already provided script files. Design a synchronous system in VHDL which controls a two-storied elevator (ground floor and first floor). You will implement it with a two-process FSM as described above. The clock signal has a frequency of 10 MHz. The circuit

    €40 (Avg Bid)
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    9 ofertas

    ...this design in VHDL and verify its correctness by writing a testbench. Simulate the design using the ModelSim simulator. What is the difference between the data type bit and the data type std_logic in VHDL? What is the difference between the data type bit_vector and the data type std_logic_vector in VHDL? What is the difference between VHDL signals and

    €26 (Avg Bid)
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    10 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €500 (Avg Bid)
    €500 Média
    1 ofertas

    Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the ot...SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

    €262 (Avg Bid)
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    11 ofertas

    You have to programming a stopwatch with an Memory function in VHDL. It has to run on a Nexy 4 - fpga Board. Best regards, Kevin

    €170 (Avg Bid)
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    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

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    Vivado Expert Encerrado left

    Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks

    €24 / hr (Avg Bid)
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    Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

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    3 ofertas

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    ...and friendly working environment - Flexible working hours - Option to learn during working hours (the 90/10 rule) WE REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture

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    I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    1 ofertas

    ...chart of source. Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information about further

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    Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.

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    Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.

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    - Need to develop bitstream for different algorithm for FPGA boards. - Developer with proven experience with FPGA Verilog. - Can able to code, simulate, synthesize and compile verilog on FPGA. - Would be great if understands concept of Blockchain technology and how it works. - Understand requirements and based on that able to prepare hardware requirements

    €14 / hr (Avg Bid)
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    Looking for an experienced programmer in Lattice FPGA's, specifically the ICE40 series. Simple project, buffer 320 bytes of data with multiple clock domains. Prefer VHDL

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    Need VHDL expert Encerrado left

    I have a VHDL code. Then It has some issue. I need to fix it within a few hours. If you are electronic expert you can do it within 1 hours. I'll send details via interviewing. Ivan.

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    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

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    I need to convert a python code to vhdl code using myhdl.i will attach the python code.

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    ...Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx ISE tools in this project. The deliverables will be: a. code b. testbenches c. measurements

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    Bug-fix Mining App and FPGA-VHDL Project. You have to fix the mining App what is written in C and running on a Linux server. And fix on the FPGA side the PLL and add multicores.

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    I would like to implement a calculator which takes inputs from the ps2 keyboard and displays them on 7 segment.

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    Tutor/Mentor Required(Online): -- Good knowledge of Embedded c/c++ and VHDL -- Good Experience with Renesas Microcontrollers and e2 Studio

    €6 / hr (Avg Bid)
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    Muktiplexer of 2 to 1 in vhdl using tje software xillinix

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    more details will be given in the chat only serious expert and my maximum budget for this task is $100

    €50 (Avg Bid)
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    24 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €912 (Avg Bid)
    €912 Média
    4 ofertas

    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [fazer login para ver a URL]; a. The source can

    €553 (Avg Bid)
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    find fpga projects Encerrado left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

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    need report on vhdl of 4 bit alu

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    Hi,eveyone.I need a signal processing coding for my work using altra quartus II and VHDL.

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    ADC
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    Matlab Codnig Encerrado left

    I need the matlab developer and verilog developer

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    Implementation of 4 bit alu in VHDL using the software Xillinix ISE I Need report on circuits diagrams, truth table, and simulations results the structure report should go by 1-introduction 2-block diagram 3-Technical Words 4-Implementations 5-Results 6-Conclusion

    €124 (Avg Bid)
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    6 ofertas
    16-point FFT Encerrado left

    verilog code for radix-4 16 point fft

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    FFT working in VHDL Encerrado left

    I want a VHDL code to achieve a N point FFT

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    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

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    Trophy icon Explanation of VHDL code Encerrado left

    I have a VHDL code.. I need someone to explain that code in detail to me.. what stuff it is doing on board..

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    Garantido
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