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VHDL project

Digital clock with Pmod OLED rgb display connected to FPGA Nexys4 DDR based on VHDL programming , including Digital clock package having the features of time sitting , alarm sitting ( on-off , a standard ringtone and flashing leds-2 LED CHASER- ) , stopwatch sitting

By default that display current date and time on two lines

Day dd/mm/yyyy : MON 17/02/2017

hh:mm:ss (AM/PM) : 11:23:55 AM

If i put the swich 1 that display : DATE SET ( nothing else displayed on the screen ) then i have 5 boutons lets say B1 B2 B3 to select day , month or year then B4 B5 to increment and decrement

Switch2 display TIME SET then by the same process B1 B2 B3 to select hour , minutes and seconds then B4 and B5 to increment and decrement

ALARM : Switch3 : on-off

Switch 4 display AlARM SET then B1 and B2 to select hours or minutes and B4 B5 to increment and decrement, in output i would love to have a standard rington BIP and 3 Led chaser ( chenillard by french )

stopwatch : switch 5 on-off , B1 play , B2 restart , B3 pause

I’m a beginner, that’s my first time ever , i will try to make a general architecture and then program it basing in VHDL so if u guess a bloc is so complicated u can suggest me a better way to do it or a better way to use switches ... or maybe something to add to my project by example 2 alarms ... thank you

I have a FPGA nexys4 DDR and Pmod OLED rgd

To connect Pmod OLED rgb i have some files ready to use i just have to declare the inputs’signals on the code ( there’s a place for that )

The link below contains the method i have the right to use To connect Pmod lcd with FPGA

[url removed, login to view]:pmodoledrgb

I need the also the state machine of the project and the general architecture of blocs ( register , counter , mux ... ) and an explanation of every bloc function ( 2 to 3 by example the bloc have for inputs the current signal and for output.. it count the value of .. that will be used for .. or it help to solve a problem which is .. )

Habilidades: Verilog / VHDL

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( 0 comentários ) France

ID do Projeto: #15590136

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ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using VHDL, also i already have the Nexys 4 board, please check my profile also please message me so that we can discuss Best regards Stay tuned, I'm st Mais

$222 USD em 3 dias
(299 Comentários)
7.6

10 freelancers estão ofertando em média $157 para esse trabalho

loi09dt1

A proposal has not yet been provided

$50 USD in 5 dias
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6.3
quandangvan

A proposal has not yet been provided

$200 USD in 7 dias
(4 Comentários)
4.1
prakashddit

have 2.5+ years of expertise

$277 USD in 7 dias
(2 Comentários)
2.0
filip992

Hello, I can help you with design, ping me so we can go over what you need and we can make adjustment to the bid. Looking forward to your reply. Relevant Skills and Experience VHDL/Verilog Proposed Milestones $111 US Mais

$111 USD in 7 dias
(1 Comentário)
1.1
Developer000

i will help with code and documentation ........................................................................................................

$30 USD in 3 dias
(0 Comentários)
0.0
sofiadubina99

Hello I have deeply knowledge about several family FPGA such as Altera, Xillinx and Lattice.. and then I can use several programming tools such as Quartus, Xillinx ISE, Lattice Diamond. Thank you Relevant Skills and Mais

$155 USD in 3 dias
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sujitdas487

I have 6 years experience in designing circuits of Fpga..where in various projects I used input output ports(pmod) interface with peripheral..specially I have already done projects on digital clock, time date etc in fp Mais

$144 USD in 7 dias
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0.0
developerstars

Okay. I understood your requirement. I think you have to implement the hand watch function using state machine in FPGA/VHDL. In this field, I have good skill. So I can complete it within 3 days. Relevant Skills and Mais

$155 USD in 3 dias
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0.0
fermatliu

Can i finish it in Verilog Not VHDL. I am familiar with FPGA。for 5 year. Work for SoC Designer

$222 USD in 15 dias
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0.0