Digital systems and verilog

Read the MPZ paper (M. Faezipour and M. Nourani, "A Customized TCAM Architecture for

Multi-Match Packet Classification," in Proceedings of the IEEE Global Telecommunications

Conference (GLOBECOM), (San Francisco, CA), pp. CAM01.1.1-CAM01.1.5, Nov. 2006.)

posted on the course webpage. Section III explains the Multi-Match Prioritizer (MPZ) unit. The

conventional (single-match) priority encoder finds only one match, i.e. the highest priority input.

An n-bit MPZ unit finds r (1 ≤ r ≤ n) matches in exactly r cycles.

Design an 8-bitMPZ using Verilog HDL description. You may use ModelSim or Quartus II

software. In your implementation, you may have a mix of behavioral and structural descriptions

for modules/components. Slight modifications of the unit, compared to those provided in Section

III are allowed.

Your report for this problem should include the Verilog code of your MPZ design and

simulation results to show the correct behavior, or any other interesting observation (e.g.

maximum clock frequency of the design)

Verilog / VHDL Design Digital Altera Quartus

ID do Projeto: #27502525

Sobre o projeto