bubble level project

Encerrado Postado há 6 anos Pago na entrega
Encerrado Pago na entrega

the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board.

In the video attached in the .zip, the operation of the project

FPGA Verilog / VHDL

ID do Projeto: #15762690

Sobre o projeto

5 propostas Projeto remoto Ativo em há 6 anos

5 freelancers estão ofertando em média $74 nesse trabalho

sourindu

A proposal has not yet been provided

$55 USD in 4 dias
(1 Comentário)
2.3
alexstyle

The offer is purely indicative and we could discuss the details by chat.

$35 USD in 10 dias
(0 Comentários)
0.0
chinhtranduc

I have experience working on FPGA kits such as Xilinx Artix 7 development board, Numato NESO,.. Relevant Skills and Experience FPGA, Verilog/VHDL, image processing, C/C++ Proposed Milestones $35 USD - please add more Mais

$35 USD em 1 dia
(0 Comentários)
0.0