ASIC and FPGA Design

Dear sir I have more than 10 years experience in digital design using FPGA, please check my profile also please message me so that we can discuss

Hello! Please contact me to discuss further. Thank you Relevant Skills and Experience Verilog/FPGA - 4+ years Machine Learning - 1 year Proposed Milestones $66 USD - Final tested code

A proposal has not yet been provided

I have well experienced in doing such kind of jobs............... Relevant Skills and Experience FPGA,ASIC Proposed Milestones $277 USD - I will do my level best

Hi, I have read and understood the project guideline. It's my pleasure to come across your project which suits my years of work experience & competency. Please send a message let's discuss further. Relevant Skills and Experience I have several years of experience in this and willing to use my experience to meet your immediate need. Please reply and give me a chance.

We're a team with accumulative experience of 12 years in VSLI industry. We've implemented so many complicated algorithms starting from idea and ending with .gds (ASIC) or .bit (FPGA)

I am new freelancer. I have good expertice on verilog. As my bachelor and masters project was verilog based. Relevant Skills and Experience I worked for three years in coding verilog. And based on BS and MS thesis i have very good skills. My both thesis were verilog coding based

I am a hard worker, have passion of knowledge ,solve the problems in the simplest way and will complete the job you give me with excellence. Relevant Skills and Experience I am graduated from AASTMT major computer engineering with GPA 3.83. I had studied VHDL and worked on vending machine project using it.

I have over ten years of experience in FPGA design with both Xilinx and Altera. I'm also fluent in VHDL and Verilog. I am certain that you will be satisfied with my work. Relevant Skills and Experience Xilinx, Altera, VHDL, Verilog, FPGA, simulation, synthesis, place and route Proposed Milestones $120 USD - Project complete

Hi, i am a design engineer in xilinx. I can write the verilog code for your requirement. Thank you