Design a reduced combinational logic circuit

Not really a code project, looking for some digital logic help with schematic drawing. : Design a code converter to convert a binary code to a 2-of-5 code. Use K-maps to reduce your circuit using the given inputs I3,I2,I1 and I0 to generate each output O4,O3,O2,O1 and O0. K-maps have been done with the following results: output 0: I3'I1'I0'+I2'I1'I0 output 1: I2'I0'+I2I1'I0 output 2: I3'I2'I1'I0+I1I0'+I1I2 output 3: I2I1'+I2I0'+I2'I1I0 output 4: I1I0+I3 Draw a schematic for each output using AND, OR, and NOT gates. If possible, share gates between schematics. 2-input gates have to be used. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Installation package that will install the software (in ready-to-run condition) on the platform(s) specified in this bid request. 3) Complete ownership and distribution copyrights to all work purchased. ## Platform just need the schematics ## Deadline information must be completed by 12:00 noon EST on 23 Sept 2002