The project is about creating a 2-Road Junction Traffic Light Controller using VHDL. A detailed explanation on how to design the traffic light controller will be provided at the start and when required.

Design, implement, and simulate a Traffic Light Controller for a junction of two roads (Road 1 and Road 2) with two traffic sets of lights as shown in Figure 1. Each road has a corresponding vehicle sensor (Road 1/2 Sensor) that needs to be triggered (active high for each vehicle detected) before the traffic lights for that road change state (otherwise they will stay at RED). You should use a Moore or Mealy finite state machine (FSM) for your design. Your submission will consist of 3 items: 1. Your VHDL source code for your design; 2. Your complete VHDL test bench; 3. This is most important, I want the whole project to be submitted at once not just individual files. You can send prototypes when done. This work has to be finished by 8th of May. Maximum by 9th. As my submission is on 10th. Secondly, you will be paid only and only when the entire project is completed. Trust me on this, I will not bail on you or mark the project as incomplete. If you do the job as required and corporate accordingly, I might pay u a bonus.