Verilog system

Part 1: Design a Verilog system that uses a block code for error management. The system should accept a 15-word block of 8-bit data words one word at a time, generate odd parity over the individual words, and even parity over the block, output each of the 15 9-bit data words, followed by the block check character. Part 2: Design a Verilog system that will accept a block of data words encoded as specified in Part 1; then check the parity for each data word and for the block. The system should output each of the 8-bit data words, issue a word error if the parity is incorrect for any word, and issue a block error if the block check word is in error.