VHDL: FIR Filter Design

Dear sir I have more than 9 years experience in digital design using vhdl , please check my profile also please message me so that we can discuss

Hello, My name is Mohamed. I have 5 years experience in VHDL and FIR filter design. I checked your project description and the word file. I can handle it and deliver it. Contact me for more details. Regards

Professional engineer with DSP experience ................................................................................................

A proposal has not yet been provided

Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TSMAC IP to reduce the overhead created in software for packet creation and detetction. CSI-2 transmitter and receiver(6months) The project is to develop CSI-2 transmitter and receiver IPs according to the mipi standards eMMC Host Controller and Device controller(3months) The project is to develop eMMC host and Device controller IP according to the JEDEC standards. Mobile camera–testing(3months) The project is to develop 3D image processing algorithms on 1K sensor from PMD technologies High resolution camera(6.5months) The project is to develop 2D and 3D image processing algorithms on 100K sensor from Infineon sensor -Test project for DDR2 accesses -Development of calibration module -Development of chain control module -Development of control signal generator -Development of Generic LUT module -Development of Divider radix-2 algorithm -Development of atan calculator -Development of MCB reader state machine Color Pipeline(15months) The project is to develop 2D and 3D image processing algorithms on Aptina sensor -Development of Generic Frame Buffer pCore -Development of data compression and data packing pCore -Development of data packing pCore Video Processing Unit(13 months) -Improvement in algorithms to reduce FPGA resource utilization and decrease latency

I can build this FIR filter but I am most used with Xilinx ISE instead of Quartus, but I can build this on Quartus too. I can create the testbench files, plot the results in Matlab, etc. I just need to understand what is this TCL file you want, which from my experience is just a script with the simulation steps (or something like it).

A proposal has not yet been provided

hi you. i think i can fit this project. i have two years exp in fpga design. so, it's ok with me. please contact me if you need more information for proposion