Expert in RISC V Programming (MIPS)

Hey, glad to meet you! -I can help you implement your project with high quality of the design techniques. -If you have any question, please don't hesitate to ask me ! ✔️ I am professionally experienced in Computer Organization with different techniques of MIPS processor (RISC Architecture) design, and programming with Assembly language (pipelining, Hazard, single-cycle, multi-cycle, multiple issue, and multi-cores), and Performance of processor, and speedup of each type. ✔️ I wish the best for you.

Hi, I am Mtech graduate and working on Hardware Description Languages Verilog and VHDL for the past 3 years. I have already designed 5 staged pipelined MIPS CPU for RISC-V instructions using verilog for one of my previous freelancer project. I have done many Digital system design projects using RTL design and FSM and had a working experience on Xilinx FPGA boards. This is going to be my fifteenth project in freelancer and i promise to deliver the best as per your need in short time. You can refer to my portfolio item "sequence detection 101" designed using finite state machines and "VHDL code" written for stepper motor control using state machines at https://www.freelancer.com/u/vinendra77 Thank you

Hi There I am efficient in Verilog VHDL Coding and have experience working with RISC cores. I can look into your project requirements. Would love to hear from you.

Hi, I am an expert in RISC-V architecture. I have worked on the latest RISC-V ISA's base, privileged and vector spec. I am fluent in RISC-V based processor's testing via assembly/C also. I have worked on RISC-V based processors with high end features. Kindly send me the details about what kind of project you have? I will be glad to be a part of it. Thanks. Saad