1- design an 8 to 3 priority encoder such that i0 has highest priority followed by i1,i2,i3,i4,i5,i6,i7
2- design an 8 bit CLA (CARRY LOCK ADDER) , SHOW DESIGN OF 1 BIT MODULE
3- GIVE EXPPRESSION FOR ALL CARRY OUTPUTS AND SOME OUTPUTS .
4-ANALYIZE THE DELAY
I did this type of projects in my engineering degree and my MS thesis is totally based on this type of projects. I thinks i am the suitable candidate for this work. I do my work with dedication and what i said i mean it.
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