Asic design - verilog/HDL code (Report)

I hold a Master's degree in Electrical Engineering with my focus area being Digital Design, and have been part of the Chip Design industry ever since. Since I specialize in Hardware Design- I have written a lot of Verilog codes and testbenches for the same. And also worked with the Synopsys Design Compiler, Cadence NC Verilog tools for the ASIC Design flow for 30nm, 65nm technology. Have worked with FPGAs too like Xilinx Spartan 6, Altera Cyclone 4 etc. So I think I understand what you need. Let me know if you need my help.

I have enough experience in Asic flow specially in digital design with verilog/HDL coding and I made tens of report along last months in my diploma so I know that I'm who you are looking for this job

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we can focus to help you in shortest time. let talk more about u prj

Greetings sir, i am an expert freelancer for this job and your 100% satisfaction is assured if you allow me to serve. Here is the reason. Why you should pick me? a) I am a very expert and have the same kind of experience of 5 years. b) I work very hard (16+ hours a day and 7 days a week) and also very fast so... it will be done very soon than most of the other providers c) And most important part is my policy: "I will give you (to my client) life time support (as long as you keep relation with me). And fix any bugs/problem without any cost. So, don't ever worry about me” Please sir, leave a reply ASAP, as I am waiting for your kind reply

Hi, In how many words do you want me to prepare the report ?I am from Electronics engg background and I have completed so many projects in electronics circuit design and report preparation etc earlier, so I can certainly do this. Lets discuss further over chat. Thanks Souvik

I am working as a lecturer at an engineering university. Subjects I am conducting classes and labs are embedded system and electrical machines. Embedded system spacily focus on FPGA, Arduino and microcontroller. I also look after final year projects of department