ECG Denoising Filter

por ahmedmohamed85

this image shows the simulation results of ECG denoising filter using Modelsim software, the filter design and the test bench was devaloped in VHDL

image of username ahmedmohamed85 Flag of Egypt Cairo, Egypt

Sobre Mim

10 year's experience in digital system design using VHDL and verilog for FPGA's and CPLD's both for Xilinx and Altera Chips. I also have 10 years experience in working with Xilinx Ise form version 6.2 to 14.7 and Altera Quarus 2 for VHDL , verilog, system verilog and ip in addition to experience in Vivado design tool, and HLS and digital design using zynq7000

$50 Dólares/hora

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