Asic Design / FPGA

A proposal has not yet been provided

Hello! I am an experienced Engineer and have been helping out many on this platform. It would be great if I could help you out. Thank you! Relevant Skills and Experience Verilog/FPGA - 3+ years Proposed Milestones $66.5 USD - Initial design $66.5 USD - Final

Hi, we can chat regarding your project Relevant Skills and Experience Electrical Engineer Proposed Milestones $77.5 USD - Milestone 1 $77.5 USD - Milestone 2

A proposal has not yet been provided

Hello, I am an electronics engineer having experience in FPGAbased system design for more than 5 years. Relevant Skills and Experience VERILOG/VHDL, FPGA, Electronics Proposed Milestones $55 USD - Verilog Code

hey, I'm experienced in Verilog and VHDL. I've worked on quartus. please get back if you need help

My handful experience in Verilog HDL coding will help me to design digital clock for you. I have implemented softcore processors in Quartus tool that will help me to complete this project. Relevant Skills and Experience Verilog Programming Altera Quatus tool experience Proposed Milestones $10 USD - Analyzing Problem statement $45 USD - Design and Implementation

I'd be happy to do this project. Relevant Skills and Experience I'm experienced in FPGA Design with Quartus tools. Proposed Milestones $38.5 USD - Block scheme in 4 days $38.5 USD - full RTL description in Verilog in 7 days Additional Services Offered $40 USD - Testbench to verify the design