Verilog Task with Icarus Verilog

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Dear sir I have more than 10 years experience in digital design using verilog please check my profile also please message me so that we can discuss Best regards

A highly-skilled FPGA engineer with 7+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. Founder of FPGA4student. Expertise: FPGA, Verilog, VHDL, Xilinx ISE, Vivado, Altera Quartus, Modelsim, Logisim, CEDAR, MIPS Assembly, PLP Tools, Qtspim, MARS, PCB Design, Altium Designer, OrCAD, PSpice, Proteus, Arduino, CMOS VLSI Design, Cadence Virtuoso, Layout XL, Digital IC Design from RTL to GDSII, Analog IC Design.

Hello! Please check my profile and reviews to know a bit about me and my work. It would be great if I could help you out.

Can you please share the specs of ALU you want? and the simulation details. I have already designed many ALU's. It can be completed within no time.

Throughout my education years, I have designed many processor datapaths and a CPU. My CPU was handling 8-bit applications such as text parsing, n-long array computation and etc. While doing those projects, I have already designed ALU blocks in VHDL. I can easily covert them into verilog. Moreover, I am writing systemverilog code everyday while i am completing the FPGA verification tasks. Therefore, I believe that my skills are totally compatible with the requirement of yours. I look forward to hear from you.

I have 13 years of professional experience in digital design and verification. So I can write the code for ALU in Verilog and simulate and verify it using Icarus Verilog.

Please share the details of the project. I am highly experienced in working on projects relevant to Verilog HDL and implementing them on FPGA development boards.