design of wallace multiplier using energy efficient adder

Dear sir I have more than 8 years experience in digital design using vhdl please check my profile also please message me so that we can discuss Best regards

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I had done MS in Digital System Design. Also i had 8+ years of experience in the field of FPGA, VHDL and Veriog HDL. Also i had worked on several multiplier like Wallace tree multiplier, Dada tree multiplier, Booth Multiplier, Modified booth Multipliers etc. I can do this task for you.

I would like to bid this job because I am really suitable for job description: First: I am an Electronics engineer who is very familiar with Mathlab/VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird. Also, I participated image processoing project: a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Also,,I implemented the image conpression (wavelet transform). Especially, I have design some adder following the wallace multiplier so I can send the code in verilog now. These are • Sklansky adder, • Ladner-Fischer adder – for the minimum depth case only, • Brent-Kung adder, • Kogge-Stone adder, • Han-Carlson adder – constructed for values k=1 and k=2 Besides, I have a Zedboard from Xilinx to verify the design. Finally, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers.. Please contact me and let me know if you want any special requirement.

I am an Electrical Engineer having specialization in Electronics and Control, teaching in Electrical Department at FAST National University Pakistan. I am also continuing my MS degree in Electrical Engineering with specialization in CONTROL. I have taught the followings courses, and also done many projects related to these subjects. 1. Control System Design & Modelling (Matlab & Simulink) 2. Digital Logic Design (Verilog, VHDL, Logisim) 3. Digital System Design (Verilog, VHDL, Logisim) 4. Computer organization & Assembly Language (8086 processor, 8051 controller, Arduino, PIC) 5. Electric Machines Design and Analysis 6. Circuit Analysis and Designe etc 7. PCB Design (Proteous AREAS + Multisim Ultiboard) I assure you, if you assign your project to me, you surely gonna work with me in future.

i am proficient in VHDL with 100 percent completion rate. Expertise in designing synthesizable constructs using VHDL and Verilog

A proposal has not yet been provided

A proposal has not yet been provided

More than 15 years of experience in Design and implementation in RTL. Would like to understand the new Adder which is requested in the project to implement the required design.

I have done research work in VLSI and have made different designs of processors using VHDL. I also have many International Conference Publications related to VHDL and have a depth knowledge in it. I can design an efficient algorithm for your requirement. Kindly give a chance. Waiting for your reply!

I have more than 10 years of professional experience in VLSI domain. I also have experience in FPGAs so I can build the circuit and test it in hardware. The specification has a mention of "Energy efficient Adder". I need some more information on that. Do you already have an adder which needs to be used in the design of multiplier or should the Adder be designed part of the multiplier design? If yes then is there any performance metrics for the "energy efficiency" calculation?

I have already an implementation of the Wallace multiplier 4bits written in VHDL. It can be updated to the bits required (not specified) and can be updated with the new adder

I am a expert in VHDL based design have developed massive pipelined design before and have worked on Custom low-latency Adder designs like CSA. Kindly specify your requirements in more details. I'm sure i can do it easily.

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