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alarm clock - Repost - open to bidding

$10-30 USD

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Publicado há quase 7 anos

$10-30 USD

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Design the control logic for an alarm clock (for simulation purposes 20ns simulation = 1 minute real time – this can be adjusted somewhat for simulation purposes). a) Use multiple input signals (alarm set input, the snooze, and the alarm time). b) The design will contain one output (Alarm_On). A logic high at the output represents the alarm being “on”. c) An input will be used to set the alarm off. d) When the simulation starts, a counting mechanism will start counting (representing/roughly simulating a clock). e) If the alarm set input signal is high, then the alarm should turn on when the count equals the preset alarm value. If at any point during the simulation the alarm set input is switched off, the alarm should turn off by the next complete clock cycle. f) If the snooze button is activated (assume that snooze is a pulse that is at least one full clock cycle in duration) the alarm should turn off and then turn back on after 5 minutes. g) Repeat snooze button simulations (pulses) should cause the same behavior in the circuit. h) If at any time the alarm set input signal goes low, the Alarm_On output should go low by the end of the next complete clock cycle. i) Clearly describe any additional rules or assumptions. Write a VHDL or Verilog code that implements the above alarm clock. Use one-hot encoding for state encoding. Verify the functionality and behavior of the circuit. Use Quartus II toolset. Submit a report containing the following: 1. A state diagram showing the implementation of your design (overview of your design, a detailed description of your approach and design process). Clearly show all the states and the conditions on which transitions occur. 2. Hardcopy of your code. 3. Hardcopy of annotated (properly labeled) waveforms that demonstrate all the required behavior. 4. RTL schematic of the design after compilation. 5. Roughly, draw the implied hardware of your code. Provide a brief comparison between the tool's RTL schematic and the implied hardware you drew. 6. Extract the highest clock frequency of your design from the compilation report.
ID do Projeto: 13561061

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11 propostas
Projeto remoto
Ativo há 7 anos

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Hello! Please check my profile/reviews to know a bit about me. It would be great if I could help you out. Thank you!
$133 USD em 3 dias
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My Whatsapp: +92 321 6624970 I am an Electrical Engineer having specialization in Electronics and Control, teaching at Electrical Department FAST National University Pakistan. I am also persuing my MS degree in Electrical Engineering with specialization in CONTROL. I have taught the followings courses, and also done many projects related to these subjects as well as related to consumer electronics products. 1. Control System Design & Modelling (Continuous, Discrete, Linear, Non-Linear, Optimal, Fuzzy Logic + Matlab & Simulink) 2. Digital System/Logic Design (Verilog, VHDL, Logisim) 3. Digital Signal Processing (MATLAB) 4. Micro-controllers (8051, Arduino, PIC) 5. Power Electronics (PSIM, MATLAB, PSpice) 6. Control of Electric Machine Drives 7. Circuit Analysis and Designe etc 8. PCB Design (Proteous + Ultiboard + Altium Designer) I assure you, if you assign your project to me, you surely gonna work with me in future. Note: I also provide the services in Mechanical Engineering Projects.
$150 USD em 3 dias
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Hi Engdipeshdp, I am competitive to this kind of task, can take good care of this project. In fact, I already done related to this job before. Let me know the best of your time so we can discuss further based on your requirements and we can move forward to the next step. Thanks, Joseph C Ocero
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i am specialist engineer working in the field of Electronic Engineering, i have 3 years of experience in digital designs mainly in verilog.
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Hi, I am a professional in ASIC development. In past I have worked on quartus-II as well. I have a very good grip on verilog FSM designing and test development. I have worked on many projects before in VLSI industry. I am interested in this work. Looking forward to work with you. `Mangal
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