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System Verilog- NOC design (8 bit split bus)

12 freelancers estão ofertando em média $26 para este trabalho

ahmedmohamed85

A proposal has not yet been provided

$30 USD em 1 dia
(239 Comentários)
7.4
$25 USD em 1 dia
(77 Comentários)
6.1
raulbehl

Hello! Please check my reviews to know a bit about me! Thank you

$24 USD in 2 dias
(20 Comentários)
4.8
$30 USD em 1 dia
(12 Comentários)
3.7
$30 USD in 2 dias
(10 Comentários)
3.8
rohi1710rohi1710

Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TS Mais

$25 USD em 1 dia
(4 Comentários)
3.8
$30 USD em 1 dia
(4 Comentários)
3.4
smk55

I am Hardware Design Engineer have done MSC system on Chip, University Southampton, UK. I have more than 10 years experience in digital design and well acquainted with ISE 14.5, NCverilog, Vivado 2013.4, Altera Quartus Mais

$25 USD em 1 dia
(4 Comentários)
3.4
abuzduga

What exactly do you require ? A verification environment ? Will you provide the design ? Or do you also want the design ?

$15 USD in 10 dias
(1 Comentário)
2.3
burhanmudassar

Over 2.5 years of experience in Verilog RTL Design, Microcontroller Projects and Algorithm Design in MATLAB in Industry and Academia. My past projects include: - PHY Layer Design on FPGA for Software Defined Radio P Mais

$25 USD em 1 dia
(0 Comentários)
0.0
dangluonghoangvu

I have module IP for CRC calculation. i think it easy with me...please contact me to get draft version about CRC. Thanks Vu

$25 USD em 1 dia
(0 Comentários)
0.0
nitulsodlan1702

Hello, I can do this project. I am expert in FPGA, VHDL, Verilog. I have done no of project on this technology. Please open your chat box for more discussion. I have 4 year experience in this field. I can do your pro Mais

$25 USD em 1 dia
(0 Comentários)
0.0