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RTL ASIC

I am looking for the following digital block to be synthesized.

An expandable memory, where I can simply edit the number of bits I would like to write to my chip. E.g. A synchronous serial to parallel converter that I can define the number of bits depending on the application.

The memory will have a data, clock, chip enable, clear line.

Habilidades: PLC & SCADA

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( 0 comentários ) United States

ID do Projeto: #11732977

3 freelancers estão ofertando em média $483 para este trabalho

loi09dt1

Please visit my profile to see my expertise. Thanks

$545 USD in 5 dias
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aghayth

Hi I guess you should define the maximum memory of your vhdl/verilog code. I mean at synthesize time. and can define a configuration register which hold the size of the memory. this register shall be written befor Mais

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