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    4,755 verilog vhdl trabalhos encontrados, preços em EUR
    Projeto de simulação em VHDL 3 dias left

    O trabalho segue em anexo, porém uma breve descrição é: O trabalho aborda a implementação de sistemas eletrônicos digitais de tempo real, destacando a necessidade de utilizar dispositivos ló...FPGAs e CPLDs, para reduzir latências e tempo de resposta. A proposta inclui o uso de interfaces adequadas, como conversores série-para-paralelo e paralelo-para-série, para gerenciar o processamento em paralelo em aplicações de filtragem e equalização, com ênfase na eficiência computacional. O projeto de simulação em VHDL, compatível com o Vivado 2015.3, envolve a configuração de parâmetros como N=8 bits, K=16 bits, e i,j=1,...,2, com a en...

    Engenharia Elétrica Eletrônica Verilog / VHDL
    €156 (Avg Bid)
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    Project for Lívia R. Encerrado left

    Boa tarde, Lívia! Gostaria de ter a sua consultoria para o meu projeto, que consiste em integrar um processador (construído em verilog) a um Gerenciador de processos. No entanto, o prazo é apertado: dia 22/02 terça-feira. Não tenho problema com pagar a mais.

    Reescrever Artigos Redação de Conteúdo Design Digital Engenharia Elétrica Eletrônica
    €46 / hr (Avg Bid)
    €46 / hr Média
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    Project for Canisio B. Encerrado left

    Boa tarde, Canisio! Gostaria de ter a sua consultoria para o meu projeto, que consiste em integrar um processador (construído em verilog) a um Gerenciador de processos. No entanto, o prazo é apertado: dia 22/02 terça-feira. Não tenho problema com pagar a mais.

    Programação C Software Integrado LaTeX Matlab and Mathematica Tradutor de Português
    €18 / hr (Avg Bid)
    €18 / hr Média
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    Project for Nilson E. Encerrado left

    Boa tarde, Nilson! Gostaria de ter a sua consultoria para o meu projeto, que consiste em integrar um processador (construído em verilog) a um Gerenciador de processos. No entanto, o prazo é apertado: dia 22/02 terça-feira. Não tenho problema com pagar a mais.

    Programação C# Programação C++ Verilog / VHDL
    €32 / hr (Avg Bid)
    €32 / hr Média
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    Project for Iaçanã I. Encerrado left

    Boa tarde, Iaçanã! Gostaria de ter a sua consultoria para o meu projeto, que consiste em integrar um processador (construído em verilog) a um Gerenciador de processos. No entanto, o prazo é apertado: dia 22/02 terça-feira. Não tenho problema com pagar a mais.

    Algoritmo Programação C Python Verilog / VHDL x86/x64 Assembler
    €6 / hr (Avg Bid)
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    Elevador duplo Encerrado left

    I need a Verilog code simulating two 7-storey elevators, where the elevator that will arrive will be the closest to the floor it was called. I can give more information about the project privately. Preciso que seja feito um código Verilog simulando dois elevadores de 7 andares, onde o elevador que chegará será o mais próximo do andar que o mesmo foi chamado. Posso dar mais informações do projeto de forma privada.

    FPGA Verilog / VHDL
    €42 (Avg Bid)
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    Project for Nilson E. -- 2 Encerrado left

    Olá Nilson E., eu vi seu perfil e gostaria de lhe oferecer meu projeto, preciso que seja feito um código Verilog simulando dois elevadores de 7 andares, onde o elevador que chegará será o mais próximo do andar que o mesmo foi chamado. Posso dar mais informações do projeto de forma privada.

    Verilog / VHDL
    €32 (Avg Bid)
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    Project for Nilson E. Encerrado left

    Olá Nilson E., eu vi seu perfil e gostaria que você me ajudasse, preciso que seja feito um código em VHDL simulando dois elevadores de 5 andares, onde o elevador que chegará será o mais próximo do andar que o mesmo foi chamado. Posso dar mais informações do projeto de forma privada, mas é basicamente isso.

    Programação C# Programação C++ Verilog / VHDL
    €29 (Avg Bid)
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    Projeto dois elevadores em QUARTUS utilizando VHDL Encerrado left

    Preciso que seja feito um código no quartus prime II em VHDL simulando dois elevadores de 7 andares, onde o elevador que chegará será o mais próximo do andar que o mesmo foi chamado. Posso dar mais informações do projeto de forma privada, mas é basicamente isso. Deve conter waveform.

    FPGA Verilog / VHDL
    €34 (Avg Bid)
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    Construa um projeto em Verilog Encerrado left

    Criar um processador em verilog, contendo as especificações citadas no pdf.

    Engenharia FPGA Java Arquitetura de software Verilog / VHDL
    €179 (Avg Bid)
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    Portar código em "C" para Vhdl / Verilog, ( placas Fpga / Spartan 6 Xillinx / Asic ) Encerrado left

    O freelancer deverá conhecer as linguagens = C / vhdl / verilog e já ter trabalhado com FPGA / ASIC Portar e otimizar um código que já tenho pronto em "c" para vhdl ou verilog esse código gera uma string de 14 / 15 dígitos, será usado uma placa fpga xillinx spartan 6 ( a empresa xillinx disponibiliza todo o ambiente necessário ). converter a string em Sha256 usando placa asic depois de convertido em sha256 compara com um sha256 informado no inicio do processo, se igual finaliza, se não reinicia o processo. Deverá ser usado a Raspberry Pi 3 para termos uma interface ( teclado e monitor ) para inserir o código inicial

    Programação C Eletrônica FPGA Microcontrolador Verilog / VHDL
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    Criar Jogo em VGA (verilog para fpga) Encerrado left

    Implementar um jogo em verilog ou vhdl em vga

    Verilog / VHDL
    €80 (Avg Bid)
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    Contratar um Assistente Virtual Encerrado left

    Jogo VGA em Verilog para FPGA

    Assistente virtual
    €88 (Avg Bid)
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    VHDL/verilog Encerrado left

    Segue trabalho em anexo

    Processamento de Dados
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    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

    FPGA Verilog / VHDL
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    Desenvolver um Software Encerrado left

    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    FPGA Verilog / VHDL
    €290 (Avg Bid)
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    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três estágios acessam componentes críticos de hardware: o CDB, as estações de reserva (nas quais ocorrem as renomeações) e as unidades funcionais. Você deverá implementar: (1) as estações de reserva, (2) os estágios do algoritmo, (3) as unidades funcionais de multiplicação/divisão e soma/subtração, (4...

    Eletrônica FPGA Microcontrolador Verilog / VHDL
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    Ethernet UDP em FPGA e SPI em FPGA Encerrado left

    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são usados para controlar LEDs que utilizem drives LPD6803, WS2801, etc. O software envia os dados (frames) através de pacote UDP para o hardware (FPGA) que recebe, armazena em buffer de memoria RAM do FPGA e então envia estes dados para os LEDs através de uma porta SPI que deve ser implementada dentro do FPGA. Monitorando e capturando os pacotes UDP que o computador envia para o FPGA fica f&aa...

    Eletrônica FPGA Verilog / VHDL
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    Parte Operativa mips multiciclo Encerrado left

    ...provenientes das chaves devem ser concatenados com 24 ‘0’s para formar uma palavra de 32 bits. Os sinais de controle m1, m2, m3, wPC, wMem, wRI devem ser associados às chaves de entrada. Um arquivo comprimido com todos os módulos VHDL do MIPS multiciclo é disponibilizado no Moodle. O código MIPS a ser carregado na memória está contido no arquivo mem.mif. Para exibição dos dados nos mostradores, utilizar os acionadores de display de 7 segmentos feito na primeira aula de laboratório. Simular o circuito no ModelSim e prototipá-lo na placa DE2-70. Escrever um testbench VHDL para simulação no ModelSim realizando as seguintes tarefas: • ler o conteúdo das inst...

    Engenharia Verilog / VHDL
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    Relógio Digital em VHLD Encerrado left

    Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do código e ficheiros de testbench até 9 de fevereiro de 2014

    Engenharia Elétrica Microcontrolador Verilog / VHDL
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    Trophy icon Need help in creating resume for RTL design engineer 4 dias left

    Project Title: Need help in creating resume for RTL design engineer Role/Position: RTL Design Engineer Skills/Experiences to Highlight: - Knowledge of RTL design principles and methodologies - Proficiency in hardware description languages such as Verilog or VHDL - Familiarity with ASIC/FPGA design flow and tools - Understanding of digital design concepts and logic synthesis - Experience with simulation and verification tools - Strong problem-solving and analytical skills - Ability to work in a team and meet project deadlines Level of Experience: Entry Level Ideal Skills and Experience for the Job: - Bachelor's or Master's degree in Electrical Engineering or related field - Coursework or projects related to RTL design - Internship or co-op experience in the field...

    Engenharia Elétrica Eletrônica FPGA Verilog / VHDL Very-large-scale integration (VLSI)
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    Trophy icon Need help in creating resume for RTL design engineer - 01/12/2023 23:10 EST 4 dias left

    Project Title: Need help in creating resume for RTL design engineer Role/Position: RTL Design Engineer Skills/Experiences to Highlight: - Knowledge of RTL design principles and methodologies - Proficiency in hardware description languages such as Verilog or VHDL - Familiarity with ASIC/FPGA design flow and tools - Understanding of digital design concepts and logic synthesis - Experience with simulation and verification tools - Strong problem-solving and analytical skills - Ability to work in a team and meet project deadlines Level of Experience: Entry Level Ideal Skills and Experience for the Job: - Bachelor's or Master's degree in Electrical Engineering or related field - Coursework or projects related to RTL design - Internship or co-op experience in the field...

    Engenharia Elétrica Eletrônica FPGA Verilog / VHDL Very-large-scale integration (VLSI)
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    Projeto ou concurso privado #37497875 4 dias left

    Por favor, Cadastre-se ou Faça Login para ver os detalhes.

    Engenharia Elétrica Eletrônica FPGA Microcontrolador Verilog / VHDL
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    NTT hardware implementation verilog 3 dias left

    Project Title: NTT hardware implementation verilog I am looking for a freelancer who can help me with the implementation of a Radix-2 NTT hardware in Verilog. Requirements: - Strong experience in Verilog programming - Knowledge of Radix-2 NTT algorithm - Familiarity with cryptography and encryption techniques The ideal candidate should: - Have experience in FPGA or ASIC technology - Be able to suggest suitable FPGA or ASIC technology for the implementation - Understand the specific requirements of cryptography in the context of NTT implementation This project is focused on the implementation of a Radix-2 NTT hardware for the purpose of cryptography. If you have the necessary skills and experience, please submit your proposal.

    Engenharia Elétrica Engenharia FPGA Microcontrolador Verilog / VHDL
    €156 (Avg Bid)
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    Rtl implement 3 dias left

    I am looking for a freelancer who can assist me with the RTL implementation for my digital circuit design project. Requirements: - Experience in digital circuit design and RTL implementation - Familiarity with Verilog programming language - Ability to work with limited guidance and rough design ideas Skills and Experience: - Proficiency in Verilog programming language - Strong knowledge of digital circuit design and RTL implementation - Ability to interpret and work with rough design ideas - Attention to detail and ability to problem-solve If you have the skills and experience required for this project, please submit your proposal.

    Engenharia Elétrica Eletrônica FPGA Microcontrolador Verilog / VHDL
    €77 (Avg Bid)
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    verilog code to synthesize and implement 2 dias left

    I am looking for an experienced Verilog coder to help me design a simple digital circuit. I have a rough idea of what I want the circuit to do, but I am open to suggestions and input from the freelancer. The ideal candidate should have experience in designing digital circuits using Verilog and be able to work with a simple level of complexity.

    Design de Circuito Eletrônica Engenharia FPGA Verilog / VHDL
    €79 (Avg Bid)
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    FPGA vhdl k-mean clustering algorithm code on zynq board 6 horas left

    Description: Create a Hardware-Software Codesign version of the k-mean clustering algorithm K-means clustering is a popular data mining algorithm that partitions n samples into k clusters (note: the k-nearest neighbor classifier algorithm used in machine learning can leverage the cluster centers produced by the k-means clustering algori...algorithms have been developed that quickly converge to a local optimum solution. We will consider one of those algorithms in this project. I have provided a C code version of the k-means clustering algorithm, and a Vivado block diagram and memory layout (explained below) that you will use as a starting point. You will need to study the C version and then decide which components to implement as a VHDL module using the BRAM (you also used BRAM in HI...

    Programação C Engenharia Elétrica Eletrônica FPGA Verilog / VHDL
    €28 - €230
    Secreto ADC
    €28 - €230
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    verilog programmer Encerrado left

    I am looking for a Verilog programmer who can assist me with designing circuits. Although I have a rough idea of the type of circuit I want, I am open to suggestions and creative input. The ideal candidate should have experience in Verilog programming and be able to design circuits efficiently and accurately. This project does not have a specific timeframe mentioned.

    Engenharia Elétrica Electronic Design Eletrônica FPGA Verilog / VHDL
    €28 (Avg Bid)
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    am looking for someone good with verilog or system verilog who can implement the following design Encerrado left

    I am looking for someone who is good with verilog and system veriliog who can do the following : The idea of this application is to equifill rectangles in individual rows based on comparing strip heights and program heights. The design should use a decoder. for example : if you have row of height strip 8, it is checking 9, and 10 so it will compare 8 and 9 and then it will compare the minimum of 8 and 9 with 10. A table on page 2 of the attached document explains these comparisons with further examples. But, each time the program should only perform 3 comparisons. The program needs to use 8 clock cycles strictly. It needs to be a design that can be optimized. It needs to fit in the top level module (M216A_TopModule (2).v) that I have attached and it needs to work for all cases in...

    Engenharia Elétrica Engenharia FPGA Matlab and Mathematica Verilog / VHDL
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    need to implement neural networks in vhdl Encerrado left

    need to implement neural networks in vhdl. More details will be shared in discussions

    Engenharia Elétrica FPGA Verilog / VHDL
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    Looking an Experienced FPGA Developer for UFS Host device -- 5 Encerrado left

    using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C

    Programação C Programação C++ FPGA Microcontrolador Verilog / VHDL
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    Vhdl code designing Encerrado left

    I'm looking for a Freelancer to help me find out VHDL code for designing crossy road game. I already have a detailed plan that I'd like to have implemented, so I need someone who can understand what I'm looking for and execute the plan quickly and accurately. This is a micro project ,so I need someone who is willing to help me to get a vhdl designing code for crossy road game. If you think you have the expertise to handle a project like this, please reach out to me and let me know how you can help. Thank you for your time and consideration.

    Altera Quartus Electronic Design FPGA Design de jogos Verilog / VHDL
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    Write on LCD 16x2 display on basys 1 FPGA with an i2c interface (PCF8574A) Encerrado left

    I am looking for a freelance developer to help me with a project involving writing to a LCD 16x2 display on a basys 1 FPGA with an i2c interface (PCF8574A). I would like the programmer to use Verilog, but I don't have experience with FPGA programming and I am open to suggestions for content and/or functionality for the display. If you have experience with FPGA programming and think you are a good fit for this project, I'd love to hear from you!

    Engenharia Elétrica Eletrônica FPGA Microcontrolador Verilog / VHDL
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    ALU and Memory Encerrado left

    I am seeking assistance with designing both an ALU and memory modules for my project. I require help with both coding and design aspects. Specific tasks for this project include: - Designing ...assistance with designing both an ALU and memory modules for my project. I require help with both coding and design aspects. Specific tasks for this project include: - Designing an ALU - Designing memory modules Ideal skills and experience for this job include: - Proficiency in VHDL programming language - Strong knowledge and understanding of ALU and memory module design - Experience in both coding and design aspects of similar projects If you have experience in designing ALU and memory modules and are proficient in VHDL programming language, I would like to discuss this project ...

    Programação C Engenharia Elétrica Engenharia FPGA Verilog / VHDL
    €95 (Avg Bid)
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    VHDL design in Lattice Diamond to be programmed and implemented in a FPGA hardware board. Encerrado left

    UART Transceiver to receive input and transmit output to and from text file. The UART transceiver has start and stop bits, no parity and has configurable baud rate. Receiver will receive a 45-bit input from a text file and placed in a fifo buffer. Input will be test vectors which will be operands for the unit in which it will be processed. The unit is already done. Fifo buffer will preferably be a DPRAM (or any type of RAM available in IPExpress that will be suitable). The unit will then get to instantiate the inputs needed from the fifo buffer. The unit will produce 21-bit output for each operation. The 21-bit output will be stored to another fifo buffer. The transmitter will then get the 21-bit output from the fifo buffer and will transmit it to an output text file where all output...

    Computer Science Eletrônica FPGA Verilog / VHDL
    €92 (Avg Bid)
    ADC
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    create a function to determine fall and output in LED with iCE40 UltraPlus and LSM6DSOX Encerrado left

    I am looking for a freelancer to create a function using Verilog that will determine falls and output them in an LED display. The function will be used with the iCE40 UltraPlus and LSM6DSOX. Requirements: - The function must be written in Verilog. - The freelancer should be familiar with the iCE40 UltraPlus and LSM6DSOX. Skills and Experience: - Strong knowledge and experience in Verilog programming. - Familiarity with the iCE40 UltraPlus and LSM6DSOX is highly preferred. I already have code for the LSM6DSOX and iCE40 UltraPlus 5K communicate through SPI. You are using LSM6DSOX (3D accelerometer and 3D gyroscope) and iCE40 UltraPlus 5K and the software lattice radiant 2023 to finish this project. Basically, all you need to do is to create a function to determine f...

    FPGA Verilog / VHDL
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    I need anyone who can give his FPGA (Verilog) project to me, and that should include the use of peripherals. Encerrado left

    I am looking for someone who can provide me with an FPGA project in Verilog within a day, which should include the use of peripherals. Here are the details: Specific Peripherals: - UART - SPI - I2C Requirements and Constraints: - No specific requirements or constraints for the FPGA project Target Application: - Any application, such as data processing, signal processing, or control systems Ideal Skills and Experience: - Proficiency in Verilog and FPGA development - Experience with integrating peripherals into FPGA projects - Knowledge of UART, SPI, and I2C protocols If you have a Verilog FPGA project that includes the use of peripherals, please reach out to me. Thank you!

    Engenharia Elétrica Eletrônica FPGA Microcontrolador Verilog / VHDL
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    FPGA VHDL Designer needed Encerrado left

    I am in need of an intermediate FPGA VHDL designer who can assist me with designing a small module. This project requires someone with experience and expertise in VHDL programming for FPGAs. Skills and Experience: - Proficiency in VHDL programming for FPGAs - Experience with designing small modules - Strong understanding of FPGA architecture and design principles The project has a tight deadline, with completion expected within the next 1-2 weeks. Therefore, it is important for the freelancer to be able to work efficiently and deliver high-quality work within this timeframe. If you have the necessary skills and experience in FPGA VHDL design, and are able to meet the project requirements within the specified timeframe, I encourage you to apply for this proj...

    Engenharia Elétrica Eletrônica FPGA Verilog / VHDL
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    DMA logger Encerrado left

    design of a VHDL synthesizable module to implement data exchange between firmware and software on a KRIA SOM module

    Eletrônica FPGA Verilog / VHDL
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    Verilog implementation for numeric calculation Encerrado left

    I would like to implement a numerical interpolation in Verilog, more information will be supplied for the candidate

    Engenharia FPGA LabVIEW Matlab and Mathematica Verilog / VHDL
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    KP4-FEC ENCODER DECODER RS(544,514) verilog RTL/testbench/documentation Encerrado left

    KP4-FEC ENCODER DECODER RS (544,514) including documentation and explanation. Verilog files and simple testbench to prove the run on Quartus II. 514 data symbols per codeword 544 data plus parity symbols per codeword Codeword size = 10 * 544 = 5440 bits Correcting capability up to 15 symbols within a codeword PAM4 modulation

    Altera Quartus Engenharia Elétrica Eletrônica FPGA Verilog / VHDL
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    Connect Camera OV7670 to Nexys 4DDR using Verilog Encerrado left

    I need a simple Verilog code (that it's not too complex, understandable for a begginer) written in Vivado which will connect camera OV7670 to board Nexys 4DDR and output video on a monitor through the VGA port. I will also need the .xdc completed based on the inputs and outputs used (constraints file) and an explanation for the code. I am looking for someone who can complete this project in 1 - 2 months. Thank you for your help!

    Engenharia Elétrica Eletrônica FPGA Verilog / VHDL
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    Fpga implementation of SHA 512 Encerrado left

    I need help with the implementation of SHA 512 on an FPGA platform. I prefer to use the Xilinx platform, and I would like the programming language to be Verilog. I need the project to be completed in 2-3 days. I know this is a short timeline but I'm confident that with the right expert, it can be done. Please let me know if you have any questions or require more information.

    Engenharia Elétrica Engenharia FPGA Microcontrolador Verilog / VHDL
    €384 (Avg Bid)
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    Beer-pong game Encerrado left

    For this project, am looking to create a system design for the game Beer-Pong using a combination of BASYS 3 and additional components compatible with BASYS 3 and VHDL. I want the system design to have a basic level of complexity with a specified deadline of 3 weeks for completion. Different components like switches, LEDs and sensors. The aim of this project is to design a system for the game Beer-Pong using BASYS 3 and components that are compatible with BASYS 3. In this project, we will be able to play advanced beer- pong. Our setup will consist of 6 cups in total, and the aim is to throw three balls out of 5 into adjacent 3 cups Balls must perform a straight line). Thus, at that point, our game differs from the classical game. Positions of the cups can be adjusted since the playe...

    Programação C Engenharia Elétrica Eletrônica Microcontrolador Verilog / VHDL
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    Axi Ethernet 1G project for Xilinx KCU116/VCU118 Encerrado left

    ...assist me with an Axi Ethernet 1G base project for Xilinx KCU116, which is a Kintex Ultrascale. Project MUST NOT CONTAIN Microblaze, only soldi VHDL code. Target Device: Target device is Kintex Ultrascale+, as KCU116 board will be the target device for the project. Intended Functionality: The main objective of this project is to develop a networking solution using Ethernet. The freelancer should be experienced in VHDL developments and in networking functionalities for Xilinx KCU116. Specific Requirements: - 1/2.5GB Axi Ethernet Core (not provided, but free trial is available by Xilinx) based - 1Gb speed required - No Microblaze or MPSoC, only VHDL code. - Configuration must be done by AXI-Lite bus (No Configuration vector) - Ethernet frames must be sent by AXI-St...

    Design de Circuito Design Digital FPGA Verilog / VHDL
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    Need to complete a VHDL Coding Encerrado left

    I am looking for an experienced VHDL coder to complete a project with an intermediate complexity level. The project requires the inclusion of specific requirements and features in the code. The timeline for this project is long-term, which means it will take more than a month to complete. Ideal skills and experience: - Proficiency in VHDL coding - Experience with intermediate level projects - Experience with SPI communication - Ability to incorporate specific requirements and features into the code - Strong understanding of project timelines and ability to work on long-term projects

    Engenharia Elétrica Eletrônica FPGA Serial Peripheral Interface (SPI) Verilog / VHDL
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    The aim of this project is to design a system for the game Beer-Pong using BASYS 3 and components that are compatible with BASYS 3 and VHDL Encerrado left

    For this project, I am looking to create a system design for the game Beer-Pong using a combination of BASYS 3 and additional components compatible with BASYS 3 and VHDL. I want the system design to have a basic level of complexity with a specified deadline of 3 weeks for completion. Different components like switches, LEDs and sensors. The aim of this project is to design a system for the game Beer-Pong using BASYS 3 and components that are compatible with BASYS 3. In this project, we will be able to play advanced beer- pong. Our setup will consist of 6 cups in total, and the aim is to throw three balls out of 5 into adjacent 3 cups ( Balls must perform a straight line). Thus, at that point, our game differs from the classical game. Positions of the cups can be adjusted since...

    Eletrônica FPGA Desenvolvimento de Jogos Arquitetura de software Verilog / VHDL
    €60 (Avg Bid)
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    Verilog code for a karastuba multiplier with parallelism Encerrado left

    Verilog code for a Karatsuba multiplier with parallelism - Desired bit width for the multiplier: 32 bits - Test-bench verification required: Yes - Specific deadline for the project: Within 1 week preferably in 3 days Ideal Skills and Experience: - Proficiency in Verilog coding - Experience in designing and implementing Karatsuba multipliers - Knowledge of parallelism in Verilog - Ability to create and execute test benches for verification - Strong understanding of digital logic and arithmetic operations

    Engenharia Elétrica FPGA LabVIEW Matlab and Mathematica Verilog / VHDL
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    Smart Home Energy Monitor Encerrado left

    Create a simple yet effective Smart Home Energy Monitor using your expertise in electrical engineering and FPGA/VHDL. This project aims to help working individuals monitor and optimize their home energy consumption. It can be both fun and practical.

    Engenharia Elétrica Eletrônica FPGA Microcontrolador Verilog / VHDL
    €97 (Avg Bid)
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    Write a Verilog code to implement the behavior of single neuron and corresponding test bench. Input signals can be only 3-4. Activation function can sigmoid function. Encerrado left

    I'm looking for an experienced engineer to write a Verilog code that implements the behavior of a single neuron. The input signals required will be 4, so the complexity should be intermediate. As for design constraints or requirements, I don't have any specific ones, but I do have some preferences for the implementation. The activation function should be a sigmoid function. Any other details, to be discussed when you bid.

    Eletrônica Engenharia Verilog / VHDL
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