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    2,325 mips verilog trabalhos encontrados, preços em EUR

    Programa simples de um trabalho para uma disciplina para fazer um programa em mips utilizando o simulador MARS . Falar no email: [REMOVED BY FREELANCER.COM ADMIN] para detalhes

    €25 (Avg Bid)
    €25 Média
    2 ofertas

    Implementar um jogo em verilog ou vhdl em vga

    €120 (Avg Bid)
    €120 Média
    6 ofertas

    Jogo VGA em Verilog para FPGA

    €132 (Avg Bid)
    €132 Média
    3 ofertas

    Segue trabalho em anexo

    €126 (Avg Bid)
    €126 Média
    10 ofertas

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

    €22 (Avg Bid)
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    3 ofertas

    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    €372 (Avg Bid)
    €372 Média
    2 ofertas

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três está...

    €404 (Avg Bid)
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    3 ofertas

    O MIPS Multiciclo utiliza uma única memória para armazenar programa e dados. A memória é endereçada pelo PC ou pelo registrador na saída da ULA, através de um multiplexador, sendo as instruções lidas da memória transferidas para o Resitrador de Instruções – RI e os dados lidos transferidos para o Re...

    €82 (Avg Bid)
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    3 ofertas

    DESCRIÇÃO A. Display gráfico mapeado em memória • O MARS oferece, dentre as suas ferramentas de apoio ao desenvolvimento de aplicações em assembler MIPS, uma janela gráfica baseada em pixels. Suas principais características são as seguintes: ‣ Resolução configurável, default 512 x 256 pixels. ‣ Ca...

    €51 (Avg Bid)
    €51 Média
    2 ofertas

    ler os caracteres digitados pelo utilizador e guardar esses caracteres numa string. Essa string será mais tarde convertida para um número inteiro. Se o utilizador tentar introduzir caracteres não-válidos (isto é, que não sejam os algarismos de 0 a 9) o programa "queixa-se" e começa tudo de novo.

    €214 - €642
    €214 - €642
    0 ofertas

    Programa: (trabalho 7) O programa deverá pedir ao utilizador um número inteiro. Em vez de  utilizar a chamada ao sistema de código 1 irá utilizar um ciclo e a chamada ao sistema de código  12 (leitura de um caracter1 ) e armazenar os caracteres digitados num array. Se o utilizador  introduzir um caracter não-válido (por exemplo, uma l...

    €264 (Avg Bid)
    €264 Média
    3 ofertas
    DSP48E1 help 4 days left

    Hi! I need some help with DSP48E1 verilog instantiation.

    €3 / hr (Avg Bid)
    €3 / hr Média
    5 ofertas
    mips assembly 3 days left

    i have a problem with mips assembly language, if you are familiar with that language send me

    €170 (Avg Bid)
    €170 Média
    6 ofertas
    MIPS program 3 days left

    They are attached. It's three files.

    €21 (Avg Bid)
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    3 ofertas
    I want clients 18 hours left

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

    €15 (Avg Bid)
    €15 Média
    2 ofertas

    We have a Spansion Flash S34ML02G100TFI00 in which the binary f...Serial number and Mac-Id need to be written in a binary file so that we can re-flash the device without affecting any of the other functionality. The Flash is controlled by a MIPS MCU. The Bidder who successfully completes this project will be awarded three more very similar projects.

    €74 (Avg Bid)
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    4 ofertas

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    €132 (Avg Bid)
    €132 Média
    7 ofertas

    Need an experienced programmer who can do basic operation in MIPS. Budget- 35$

    €31 (Avg Bid)
    €31 Média
    4 ofertas

    Hello, i want a small atm software written in mips assembly language; Really basic software, login, deposit and cash out.

    €86 (Avg Bid)
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    2 ofertas

    ...i am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

    €33 (Avg Bid)
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    112 ofertas

    verilog coding using putty or terminal. if you are interested i will give more information.

    €116 (Avg Bid)
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    27 ofertas

    I want help with system Verilog coding. I have a working code that I want revised a bit.

    €89 (Avg Bid)
    €89 Média
    9 ofertas

    mtech Verilog project

    €18 (Avg Bid)
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    19 ofertas

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    €154 (Avg Bid)
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    7 ofertas

    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

    €2423 (Avg Bid)
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    15 ofertas

    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

    €92 (Avg Bid)
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    12 ofertas

    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

    €86 (Avg Bid)
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    2 ofertas

    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    €17 / hr (Avg Bid)
    €17 / hr Média
    9 ofertas

    Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am

    €112 (Avg Bid)
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    12 ofertas

    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

    €3798 (Avg Bid)
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    27 ofertas

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    €334 (Avg Bid)
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    3 ofertas

    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

    €56 (Avg Bid)
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    18 ofertas

    FPGA TCPIP implementation using Verilog

    €18 / hr (Avg Bid)
    €18 / hr Média
    16 ofertas

    Verilog digital logic deisgn simple work

    €20 (Avg Bid)
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    18 ofertas

    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [login to view URL]

    €39 (Avg Bid)
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    16 ofertas

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

    €20 (Avg Bid)
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    21 ofertas

    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

    €19 (Avg Bid)
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    17 ofertas

    Compile the redir linux tool ([login to view URL]) for Openwrt 15.05.1 MIPS ar71xx architecture. Not necessary a .ipk package, just a executable.

    €51 (Avg Bid)
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    4 ofertas

    Hi Muhammad Nauman Z., I noticed your profile and would like to offer you my project. We can discuss any details over chat. I have to short questions which i need to answer...noticed your profile and would like to offer you my project. We can discuss any details over chat. I have to short questions which i need to answer, converting c language to MIPS

    €34 (Avg Bid)
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    1 ofertas

    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

    €18 / hr (Avg Bid)
    €18 / hr Média
    20 ofertas

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    €112 (Avg Bid)
    €112 Média
    19 ofertas

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    €104 (Avg Bid)
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    13 ofertas

    We are looking for a System Verilog Training for few Engineers in our premises.

    €1702 (Avg Bid)
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    5 ofertas

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    €86 (Avg Bid)
    €86 Média
    8 ofertas

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    €104 (Avg Bid)
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    19 ofertas

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    €158 (Avg Bid)
    €158 Média
    15 ofertas

    Teach me the concepts of Mips and Intel assembly

    €16 (Avg Bid)
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    1 ofertas

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    €74 (Avg Bid)
    €74 Média
    5 ofertas

    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    €91 (Avg Bid)
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    11 ofertas

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    €113 (Avg Bid)
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    7 ofertas