Mips verilog trabalhos

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    2,445 mips verilog trabalhos encontrados, preços em EUR
    Assembly mips Encerrado left

    Trabalho em assembly mips em português

    €26 (Avg Bid)
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    6 ofertas

    Programa simples de um trabalho para uma disciplina para fazer um programa em mips utilizando o simulador MARS . Falar no email: [REMOVED BY FREELANCER.COM ADMIN] para detalhes

    €26 (Avg Bid)
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    Implementar um jogo em verilog ou vhdl em vga

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    6 ofertas

    Jogo VGA em Verilog para FPGA

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    3 ofertas
    VHDL/verilog Encerrado left

    Segue trabalho em anexo

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    10 ofertas
    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

    €23 (Avg Bid)
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    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    €384 (Avg Bid)
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    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três está...

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    O MIPS Multiciclo utiliza uma única memória para armazenar programa e dados. A memória é endereçada pelo PC ou pelo registrador na saída da ULA, através de um multiplexador, sendo as instruções lidas da memória transferidas para o Resitrador de Instruções – RI e os dados lidos transferidos para o Re...

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    DESCRIÇÃO A. Display gráfico mapeado em memória • O MARS oferece, dentre as suas ferramentas de apoio ao desenvolvimento de aplicações em assembler MIPS, uma janela gráfica baseada em pixels. Suas principais características são as seguintes: ‣ Resolução configurável, default 512 x 256 pixels. ‣ Ca...

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    ler os caracteres digitados pelo utilizador e guardar esses caracteres numa string. Essa string será mais tarde convertida para um número inteiro. Se o utilizador tentar introduzir caracteres não-válidos (isto é, que não sejam os algarismos de 0 a 9) o programa "queixa-se" e começa tudo de novo.

    €221 - €664
    €221 - €664
    0 ofertas

    Programa: (trabalho 7) O programa deverá pedir ao utilizador um número inteiro. Em vez de  utilizar a chamada ao sistema de código 1 irá utilizar um ciclo e a chamada ao sistema de código  12 (leitura de um caracter1 ) e armazenar os caracteres digitados num array. Se o utilizador  introduzir um caracter não-válido (por exemplo, uma l...

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    ...-Programming Language : Verilog HDL. -This project is divided to two parts:- Part 1. Design and implement a 32 bit architecture pipelined CPU with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x

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    verilog counter 5 dias left

    need to use Quratz 18.1 to create and simulate a 5 bit counter.

    €55 (Avg Bid)
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    7 ofertas

    I am a Verilog beginner. Need help in instantiating a LUT based memory. The requirements are stated in the [fazer login para ver a URL] file.

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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €167 - €502
    €167 - €502
    0 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

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    Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

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    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

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    c++, mars, mips Encerrado left

    c++ , mars simulator, mips ,asembly

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    Vivado Expert Encerrado left

    Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks

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    Home Automation PCB Encerrado left

    ...com/controllers/veraplus/ link where you can see the working abilities of the PCB board I need the design with working prototype, send me quote with prototype. Hardware CPU: 880MHz MIPS SoC Flash Memory: NAND 128MB Memory: DDR3 256MB Z-Wave: Z-Wave Plus ZigBee: HA 1.2 Bluetooth: 4.0 + BLE Wi-Fi: 802.11 a/b/g/n/ac USB Port: USB 2.0 WAN Port: Gigabit Ethernet

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    Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    ...and friendly working environment - Flexible working hours - Option to learn during working hours (the 90/10 rule) WE REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture

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    I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    ...Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information about further requirements (some

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    - Need to develop bitstream for different algorithm for FPGA boards. - Developer with proven experience with FPGA Verilog. - Can able to code, simulate, synthesize and compile verilog on FPGA. - Would be great if understands concept of Blockchain technology and how it works. - Understand requirements and based on that able to prepare hardware requirements

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    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

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    I need to convert a python code to vhdl code using myhdl.i will attach the python code.

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    ...Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx ISE tools in this project. The deliverables will be: a. code b. testbenches c. measurements

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    more details will be given in the chat only serious expert and my maximum budget for this task is $100

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    24 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €912 (Avg Bid)
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    4 ofertas

    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [fazer login para ver a URL]; a. The source can

    €553 (Avg Bid)
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    find fpga projects Encerrado left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

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    I provide a cross-compilation toolchain, help me compile PJSIP-2.8, require support for WebRTC, video CC=mips-openwrt-linux-gcc ./configure --host=mips-openwrt-linux --build=x86_64-linux-gnu --prefix=/home/pjvideo --disable-libyuv Just need to compile, do not need to make other changes, send the compiled file to me, if you can

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    please check the attach file if you can read the files and modify thats fine for me or you have to create same way file for me if you can then bid

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    Matlab Codnig Encerrado left

    I need the matlab developer and verilog developer

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    I need help with someone putting me through with mIPS. The person needs to be an expert at it and needs to be available.

    €27 (Avg Bid)
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    1 ofertas

    I need help with someone putting me through with mIPS. The person needs to be an expert at it and needs to be available.

    €31 (Avg Bid)
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    1 ofertas

    I need help with someone putting me through with mIPS. The person needs to be an expert at it and needs to be available.

    €6 - €19
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    0 ofertas

    I need help with someone putting me through with mIPS. The person needs to be an expert at it and needs to be available.

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    MIPS Expert needed Encerrado left

    I need help with someone putting me through with mIPS. The person needs to be an expert at it and needs to be available.

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    This is a small project about MIPS assembly. The details may be discussed on PM. This program is to be worked on MARS program.

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    mips assembly Encerrado left

    need some help in mips assembly and detailed explanation as well.

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    16-point FFT Encerrado left

    verilog code for radix-4 16 point fft

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    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

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